1. Field of the Invention
The present invention relates to a method for forming a pattern of a stacked film, and more particularly, to a method for forming a stacked film composed of a polysilicon film and an upper oxide film, which are formed on a lower oxide film.
2. Description of the Related Art
FIGS. 1A and 1B and FIGS. 2A and 2B illustrate schematic views of two-layer structures, each of which is composed of a polysilicon film and an upper oxide film for fabricating a conventional thin film transistor. FIG. 1A is a plan view of a two-layer structure, and FIG. 1B is a cross-sectional view obtained by cutting the two-layer structure of FIG. 1A along the line I—I. FIG. 2A is a plan view of a two-layer structure, and FIG. 2B is a cross-sectional view obtained by cutting the two-layer structure of FIG. 2A along the line II—II.
In each case, the lower oxide film (SiO2) 502 is deposited on the glass substrate 501 with a thickness of approximately 300 nm. Next, the silicon film 503 and the upper oxide film 504, which configure the two-layer structure, are deposited on the lower oxide film 502 with thicknesses of 60 m and 10 nm, respectively. Subsequently, the silicon film 503 is crystallized by an excimer laser, thus forming a polysilicon (poly-Si) film.
Next, dry etching is conducted simultaneously for the silicon film 503 and the upper oxide film 504, which configure the two-layer structure, followed by formation of the side face of the two-layer structure of the polysilicon film 503 with the thickness of 60 nm and upper oxide film 504 with the thickness of 10 nm at an angle of approximately 90° (vertical shape) with respect to the glass substrate.
The reason that the two-layer structure is composed of the polysilicon film and the upper oxide film is to protect the surface of the polysilicon film, which is an active layer, and keep the same surface clean. In addition, the reason that the film thicknesses in the two-layer structure are set at 60 nm for the upper oxide film and 60 nm for the polysilicon film is for thinning the film thickness of the upper oxide film as much as possible and facilitating the formation of the two-layer structure by dry etching. Detailed contents of this will be described later in a section of a method for forming a two-layer structure.
After the formation of the two-layer structure described above, high-concentration phosphorus ions are doped into the polysilicon film in the two-layer structure, thus forming a source/drain (not shown). Subsequently, low-concentration phosphorus ions are doped, thus forming a lightly doped drain (LDD). Thereafter, the gate oxide film 505 is formed in a thickness of 45 nm, followed by deposition of a two-layer film formed of a micro-crystalline silicon (μc-Si) film 506 and the Cr film 507. Then, the two-layer film is etched, thus forming the gate electrode 521. As the gate electrode 521, the Cr film 507 made of a metal with a high melting point is used because of its outstanding ability to resist heat, as well as its low electric resistance. Moreover, the μc-Si film 506, which has a specific work function, is used as an interlayer film because of its easiness in controlling threshold values. For the high melting point metal utilized as a gate material, W, Mo, Ti, Ta or a silicide film of any of these can be used as well as Cr. Thereafter, a heat treatment at a temperature of 350° C. or more is conducted, thus activating impurities contained in the polysilicon film of the two-layer structure, into which the phosphorus is doped. Thus, the electric resistance of the polysilicon in the portion into which the phosphorus is doped is lowered.
After the steps described above, a protective oxide film (not shown) is further deposited in a thickness of 300 nm. Then, a contact to communicate with the polysilicon film in the activated two-layer structure is opened in the protective oxide film and the gate oxide film, and Al wiring is formed thereon. Thus, a desired thin film transistor is obtained.
Next, a method for forming the foregoing two-layer structure will be described with reference to cross-sectional views of FIGS. 3A to 3C.
As a method for etching the foregoing upper oxide film and polysilicon film, a gas containing CF4 and O2 is used, and the entire upper oxide film 604 and a part of the polysilicon film 603 are simultaneously etched by reactive ions, using the photoresist 608 as a mask. The etching conditions in this case are set as:
Gas mixture ratio: CF4:O2=4:1
RF power: 700 W
In these etching conditions, the foregoing two-layer structure is etched close to vertically.
The residual polysilicon film is etched under the following etching conditions by use of the gas containing CF4 and O2:
Gas mixture ratio: CF4:O2=4:1
RF power: 300 W
Specifically, the RF power in the above conditions is lowered than that in the initial etching conditions. In this type of low RF power condition, an etching rate for the polysilicon film 603 is higher than that for the lower oxide film 602. Thus, the etching for the lower oxide film is restricted to the minimum. However, in this case, the etching rate for the upper oxide film on the polysilicon film 603 is simultaneously slowed. Hence, at the time when the etching for the polysilicon film is completed, the polysilicon film is over-etched in the lateral direction with respect to the upper and lower oxide films, and the upper oxide film 604 is formed into a shape overhanging the polysilicon film 603.
In addition, after forming the two-layer structure, its surface is cleaned by a diluted hydrofluoric acid treatment for approximately 10 seconds, followed by deposition of the gate oxide film. The overhang of the oxide film, which is formed by etching the polysilicon film, can be removed by etching using the diluted hydrofluoric acid treatment because the film thickness of the upper oxide film is 10 nm. Because the etching rate by the diluted hydrofluoric acid treatment is several nm/min, the portion of the oxide film, which hangs during the work of immersion of the substrate for 10 seconds and pull-up thereof, is removed by etching from the upper and lower sides thereof. Hence, it is necessary to thin the film thickness of the two-layer structure to 10 nm (60 nm for the polysilicon film). If the film thickness of the upper oxide film is thickened more than 10 nm, then the time necessary for the diluted hydrofluoric acid treatment, required for removing the overhang, must be more than 10 seconds, and an excessive etching of the lower oxide film occurs on an interface between the polysilicon film and the lower oxide film. In addition, if the polysilicon film is thickened to more than 60 nm, then variations in etching in the case of selectively removing the polysilicon film by etching are increased, thus making it difficult to control the dimension of the polysilicon film and to switch off the TFT.
As described above, if the conventional process is used, then the excessive etching of the lower oxide film has hardly occurred under the polysilicon film, and the two-layer structure has been formed such that its side face can be close to vertical.
As shown in FIG. 2B which is the cross-sectional view obtained by cutting the plan view of FIG. 2A, the conventional two-layer structure is formed into a shape in which the side faces of the upper oxide film 504 and polysilicon film 503 are close to vertical with respect to the base.
Hence, if the three-layer film formed of the gate oxide film 505, the micro-crystalline silicon film 506 for the gate electrode and the Cr film 507 is deposited on the two-layer structure, the three-layer film is thickened on the two-layer structure and the lower oxide film excluding the same on the two-layer structure, and thinned on the sidewall portion of the two-layer structure. This means that the three-layer film does not sufficiently cover the sidewall step portion of the two-layer structure. As a result, a, stress concentrates upon the three-layer film located on the sidewall of the two-layer structure, and the crack 515 occurs on the three-layer film. If the crack 515 exists on the three-layer film, then there is a possibility that a short-circuit of the gate electrode will occur in the portion of the crack 515 when the impurities contained in the polysilicon film in the two-layer structure are activated by use of a laser. Particularly, in the case of composing the gate electrode from a high melting point metal of a columnar structure, such as Cr, as in the present invention, the structure is weak against stress, and the crack 515 is more prone to occur.
In general, the surface of the polysilicon film configuring the two-layer structure is uneven, and its morphology is bad. Therefore, it is thought that the gate oxide film and the gate electrode on the two-layer structure are not evenly deposited and that the cracks become prone to occur on the thin portions of the gate oxide film and gate electrode.